1. Field of the Invention
The present invention relates to a semiconductor device including a MOS transistor, in which the mobility of electrons or holes is varied, for example, by applying a stress to a semiconductor layer.
2. Description of the Related Art
It is conventionally known that if a stress is applied to a substrate (or a semiconductor layer) in which a MOS transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) is provided, the mobility of electrons or holes is enhanced.
In the case of an nMOS transistor, if a tensile stress is applied in the channel direction, the mobility of electrons is enhanced. For instance, there is known a semiconductor device in which a liner silicon nitride film (SiN) is deposited on a silicon substrate and a stress is applied to the substrate from outside (see, e.g. S. Thompson et al., “A 90 nm Logic Technology Featuring 50 nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 um2 SRAM Cell,” IEDM Tech. Dig., 2002, pp. 61-64). In this structure, however, only a tensile stress is applicable to the substrate. Thus, the effect is obtained with respect to only an nMOS transistor.
On the other hand, in the case of a pMOS transistor, if a compressive stress is applied in the channel direction, the mobility of holes is enhanced. For example, source/drain regions of the transistor are etched to form trenches. In the trenches, silicon germanium (SiGe) is epitaxially grown and buried, and a stress is applied to the substrate (see, e.g. T. Ghani et al., “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” IEDM Tech. Dig., 2003, pp. 978-980). In this structure, however, only a compressive stress is applicable to the substrate. Thus, the effect is obtainable with respect to only a pMOS transistor.
Further, as an example of a technique in which a stress is applied to both the nMOS and pMOS, there is known a semiconductor device using a so-called “strained silicon (Si) substrate” (see, e.g. J. L. Hoyt et al., “Strained Silicon MOSFET Technology,” IEDM Tech. Dig., 2002, pp. 23-26). In this semiconductor device, an epitaxially grown silicon germanium (SiGe) layer is provided on the silicon substrate. Taking advantage of the fact that the lattice constant of silicon germanium is greater than that of silicon, a stress is applied to the silicon substrate.
In this semiconductor device, however, a stress is always applied to the silicon substrate by the silicon germanium, and defects occur in the silicon substrate in order to release the stress. The density of defects is, e.g. 1E5/cm2 or more. If such defects are present in the depletion layer, the defects function as centers of generation of current, leading to generation of junction leak current.
In general, the concentration of germanium (Ge), which is necessary for formation of the silicon germanium, is about 20%, and the effect is obtainable only for an nMOS in this case. If a similar effect is to be obtained for a pMOS, the concentration of germanium (Ge) needs to be raised to 30% or more. If the germanium concentration is raised to 30% or more, however, the thickness of a silicon (Si) layer, which can be grown on the silicon germanium (SiGe) layer, becomes 10 nm or less, and it is difficult to form a p-type MOSFET. Thus, if nMOS's and pMOS's, to which stress is applied, are to be fabricated on the same substrate, the number of defective devices would increase and the yield of manufacture of LSIs would decrease.